A silicon-oxide-nitride-oxide-silicon (SONOS) memory device has a similar structure to a metal-oxide-semiconductor (MOS) transistor and utilizes an insulating layer having a multi-layer structure as a gate insulating layer. The insulating layer may, for example, include a tunnel insulating layer, a charge trapping layer and a blocking insulating layer. The charge trapping layer is conventionally formed of silicon nitride. The SONOS memory device may write or erase information using Fowler-Nordheim tunneling (F-N tunneling) or hot carrier injection. U.S. Pat. No. 5,768,192 to Eitan entitled “NON-VOLATILE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING” relates to writing or erasing information by hot carrier injection.
FIG. 1 is a cross-sectional view showing a conventional SONOS memory cell.
Referring to FIG. 1, a conventional SONOS memory cell includes source and drain regions 12 and 14 formed in a semiconductor substrate 10 and a gate electrode 22 formed on a channel region defined in the semiconductor substrate 10 between the source and drain regions 12 and 14. An insulating layer having a multi-layer structure is disposed between the gate electrode 22 and the semiconductor substrate 10 and includes a tunnel oxide layer 16, a charge trapping layer 18 and a blocking insulating layer 20.
When ground, gate and drain voltages are applied to the source region 12, the gate electrode 22 and the drain region 14, respectively, accelerated or hot charge carriers develop in the channel region near the drain region 14 and electrons or holes are trapped in a charge storage region 24. The polarity of the gate and drain voltage, can define a charge storage region 24 where electrons are trapped.
In the conventional SONOS memory cell, a charge storage region is not defined, but determined depending on the region where hot carrier injection occurs. Therefore, if the region where electrons are injected is different from the region where holes are injected, threshold voltage can vary due to repeating writing or erasing cycles. In addition, the charge trapping layer 18 where the electrons are trapped is positioned between the charge storage regions 24, such that electrons with thermal energy move parallel along the charge trapping layer 18. Therefore, data identification between the two charge storage regions 24 is deteriorated. Further, because an area of the charge trapping layer 18 is determined by a photolithographic process, distribution of a trap site can increase.